The present invention relates generally to a semiconductor memory device, and more particularly to an electrostatic discharge protection circuit that protects an internal circuit of a semiconductor memory device from electrostatic discharge.
In general, when a semiconductor integrated circuit comes into contact with a charged human body or machine, an excessive current having a large amount of energy may cause extensive damage to an internal circuit of the semiconductor device. This excessive current is charged in the human body or the machine and is discharged to the internal circuit of the semiconductor device through an external pin and an input/output pad as static electricity. An external circuit may also be damaged as the static electricity charged in the internal circuit flows out through the machine due to the contact with the machine.
Accordingly, most semiconductor integrated circuits include an electrostatic discharge protection circuit between the input/output pad and the internal circuit to prevent damage to the main circuit.
The electrostatic discharge protection circuit may include various devices. A grounded-gate NMOS transistor is primarily used where an NMOS transistor is used as the electrostatic discharge protection circuit.
The input/output pad is coupled with a drain of the NMOS transistor. When a voltage level of the drain is increased due to static electricity, an avalanche breakdown is generated between the drain of the NMOS transistor and a substrate to allow electrostatic current to flow to the substrate.
When a voltage level of the substrate increases higher than a source voltage level of the NMOS transistor due to the electrostatic current that flows to the substrate, the electrostatic current is discharged from the drain to the source of the NMOS transistor according to the bipolar junction transistor (BJT) properties of the NMOS transistor.
However, the electrostatic discharge effect according to the BJT properties of the NMOS transistors not a superior method of discharge because of the driving ability limitations of the NMOS transistor. Therefore, a method of enhancing the driving ability of the NMOS transistor by applying bias to the gate of the NMOS transistor has been disclosed in the conventional art.
An example of a conventional method of enhancing the driving ability of the NMOS transistor is shown in FIG. 1. Shown in FIG. 1 is an electrostatic discharge protection circuit that drives an NMOS transistor N1 using a voltage drop by a diode chain 12 having a plurality of serially coupled diodes and a resistor R1.
When static electricity is generated at a pad 10, the static electricity is discharged from the pad 10 through the NMOS transistor N1 to a ground voltage line VSS according to the BJT properties of the NMOS transistor N1. The NMOS transistor N1 is turned on by the diode chain 12 and the resistor R1. Therefore, the driving ability of the NMOS transistor N1 is enhanced.
The conventional electrostatic discharge protection circuit may also include a diode D1 coupled between the gate of the NMOS transistor N1 and the ground voltage line VSS to form an additional path to transfer the static electricity generated in the pad 10 to the ground voltage line VSS.
However, since the conventional electrostatic discharge protection circuit in which the static electricity discharge path is formed between the pad 10 and the ground voltage line includes the diode chain 12, the resistor R1 and the diode D1 for enhancing the performance of electrostatic discharge, the layout area of the electrostatic discharge protection circuit is unwontedly increased.
In order to provide various electrostatic discharge paths, a general electrostatic discharge protection circuit also includes an electrostatic discharge protection device (not shown) coupled between the pad 10 and a power voltage line (not shown) and an electrostatic discharge protection device (not shown) coupled between the power voltage line and the ground voltage line VSS.
If the electrostatic discharge protection devices are also coupled to the conventional electrostatic discharge protection circuit, the layout area is problematically increased due to the existing diode chain 12, the resistor R1 and the diode D1 as well as the two added electrostatic discharge protection devices.